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lsis for facsimile 1 publication date: november 2001 sde00009bem MN86075 facsimile image-processing ic overview the MN86075 is a facsimile image-processing ic that receives the analog signal from an image sensor, which performs a wide range of signal-processing operations on that data to create images with enhanced quality. the MN86075 reproduces high-quality images by applying 64-level halftone processing and two-dimensional mtf correction. features ? image processing for high-quality image reproduction ? both white and black shading correction for all pixels error diffusion processing to reproduce 64-level halftone images arbitrary gamma curves can be set up. two-dimensional mtf correction for text enhancement multivalued smoothing removes jagged edges of slanted lines due to magnification and resolution conversion. enlargement and reduction (line density conversion) without moire patterns and with arbitrary magnification factors. ? implements the high processing speed of 0.5 ms/line for a3 size at 400 dpi at an image-processing clock frequency of 12.5 mhz. ? integrates offset correction, gain correction, and 8-bit a/d converter analog signal-processing circuits on the same chip. ? generates drive signals for all major image sensor types (ccd and cis). ? provides an extensive set of memory interface functions to support a wide range of applications. standard g3 (l mode) fax (200 dpi, 1.5 ms/line) b4 size document image acquisition: 64k sram (64k-bit) 1 a3 size document image acquisition: pseudo sram (256k-bit) 1 high-speed g3 (m mode) fax (200 dpi, 0.6 ms/line) b4 or a3 size document image acquisition: sram (64k-bit) 2 high-resolution g3 (m mode) fax (400 dpi, 1.2 ms/line) b4 size document image acquisition: sram (64k-bit) 2 a3 size document image acquisition: sram (64k-bit) 2 + sram (16k-bit) 2 or sram (256k-bit) 2 ultrahigh-speed g4 (h mode) fax (400 dpi, 0.5 ms/line) b4 or a3 size document image acquisition: sram (64k-bit) 4 + fifo (5k 8-bit) 1 ? 5 v single-voltage power supply applications ? image acquisition and processing for facsimile and image scanner maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
MN86075 2 sde00009bem pin arrangement (h mode) 1 vss1 2 nhrsta 3 mack 4 mbd6 5 mbd5 6 mbd4 7 mbd3 8 mbd2 9 mbd1 10 mbd0 11 hmsd7 12 hmsd6 13 hmsd5 14 hmsd4 15 hmsd3 16 hmsd2 17 hmsd1 18 hmsd0 19 ofout1 20 ofhc1 21 ofout2 22 ofhc2 23 vinig2 24 agdr2 25 agur2 26 agout2 27 fetg2 28 fets2 29 fetd2 30 vdd2 31 adin2 32 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 adin1 hmawr hmod0 hmod1 hmod2 hmod3 hmod4 hmod5 hmod6 hmod7 mast mcm0 mcm1 fsg fck1 fck2 fr1 fr2 sentim nsync nmclki d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 c80_68 vss3 64 vdd3 63 ncs 62 nrd 61 nwr 60 nreset 59 vpd0 58 vpd1 57 vpd2 56 vpd3 55 vpd4 54 vpd5 53 vpd6 52 vpd7 51 vsda 50 vsck 49 dreq 48 ndack 47 nvreq 46 abc 45 clamp 44 npeak1 43 npeak2 42 vinig1 41 agdr1 40 agur1 39 agout1 38 fetg1 37 fets1 36 fetd1 35 vrefl 34 vrefh 33 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 vss2 hmswr nhfwe nhrstr nhrstw hrck hmwe hmcwr hmbwr hwck hmid7 hmid6 hmid5 hmid4 hmid3 hmid2 hmid1 hmid0 mcd6 mcd5 mcd4 mcd3 mcd2 mcd1 mcd0 mad6 mad5 mad4 mad3 mad2 mad1 mad0 vdd1 (top view) note) the above pin-arrangement shows a pin-name of h mode, that is often utilized compared with other modes. maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
MN86075 3 sde00009bem pin descriptions 1. mode description (3 pins) pin name i/o pin no. function mast i 87 clock period selection high: master mode in master mode, the ic operates in synchronization with the internal sync signal. the internal sync signal is output from the nsync pin. low: slave mode in slave mode, the ic operates in synchronization with the external sync signal. the external sync signal is input to the nsync pin. mcm0 i 86 memory interface selection mcm1 i 85 the levels applied to these pins select the memory interface pin functions. the master clock (nmclki pin input) frequency conditions are selected by the under table. mast mcm1 mcm0 memory interface mode clock mode low low low l mode slave f ckvd 16 low low high m mode slave f ckvd 8 low high low h mode slave f ckvd 2 low high high t mode slave f ckvd 2 high low low l mode master f ckvd 16 high low high m mode master f ckvd 8 high high low h mode master f ckvd 2 high high high dctest ? l mode (low-speed mode) memory organization: pseudo sram (256k) 1 or sram (256 k) 1 recommended image signal frequency (f ckvd ): 2.0 mhz (maximum) master clock frequency (f mclki ): f ckvd 16 m mode (medium-speed mode) memory organization: sram (64k) 3 or sram (64k) 2 (no black correction or enlargement processing) recommended image signal frequency (f ckvd ): 4.0 mhz (maximum) master clock frequency (f mclki ): f ckvd 8 h mode (high-speed mode) memory organization: sram (64k) 4 plus fifo (5k 8-bit) 1 recommended image signal frequency (f ckvd ): 12.5 mhz (maximum) master clock frequency (f mclki ): f ckvd 2 t mode (test data input mode) inputs data used to test the internal ic functions. master clock frequency (f mclki ): f ckvd 2 maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
MN86075 4 sde00009bem pin descriptions (continued) 1. mode description (3 pins) (continued) pin name i/o pin no. function mcm0 i 86 dctest mode mcm1 i 85 sets the output pins and the i/o pins to the dc test mode. (continued) hmid0 hmid1 dc test function 0 * output high-impedance test 1 0 output low test 1 1 output high test * : don't care 2. system interface pins (15 pins) pin name i/o pin no. function d0 to d7 i/o 76 to 69 cpu data bus i/o a0 i 68 cpu address input a1 67 ncs i 63 cpu chip select input nwr(ds) i 61 cpu data write input (c80 to c68 pin: high) cpu data strobe input (c80 to c68 pin: low) nrd(r/w) i 62 cpu data read input (c80 to c68 pin: high) cpu data read/write input (c80 to c68 pin: low) c80 to c68 i 66 cpu selection low: 68000 family cpu high: 80x86 family cpu nreset i 60 system reset input maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
MN86075 5 sde00009bem pin descriptions (continued) 3. clock pins (2 pins) pin name i/o pin no. function nmclki i 77 master clock input clock frequency: image signal frequency 2 (memory interface mode h) image signal frequency 8 (memory interface mode m) image signal frequency 16 (memory interface mode l) clock duty: 50 % nsync i/o 78 clock period signal i/o line 1 start timing pulse mast sysl (tim2 reg) low * sync input high 1 sync output * : don't care nmclko o internal master clock output outputs the internal master clock (the nmclki pin input). mast sysl (tim2 reg) high 0 mclk output nmclki nsync(o) nsync(i) maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
MN86075 6 sde00009bem pin descriptions (continued) 4. sensor interface pins (6 pins) pin name i/o pin no. function fck1 o 83 ccd : 1 (tim1 reg) reduced ccd sensor 1 clock: ckvd1/2 sclk o ccd : 0 (tim1 reg) cds or bipolar sensor sclk clock: nckvd fck2 o 82 ccd : 1 (tim1 reg) reduced ccd sensor 2 clock: ckvd1/2 nsclk o ccd : 0 (tim1 reg) cds, bipolar sensor sclk clock: ckvd fsg o 84 ccd : 1, conta : * (tim1 reg) reduced ccd sensor sg st o ccd : 0, conta : 0 (tim1 reg) bipolar sensor st (start pulse) nstpl o ccd : 0, conta : 0 (tim1 reg) cds sensor stpl (start pulse) fr1 o 81 frm2 : 0 reduced ccd sensor r1 clock (parallel mode) frm2 : 1 reduced ccd sensor r clock (serial mode) fr2 o 80 frm2 : 0 reduced ccd sensor r2 clock (parallel mode) frm2 : 1 reduced ccd sensor sp clock (serial mode) sentim o 79 sensor timing output stm1 stm0 setim output signal (tim2 reg) (tim2 reg) 0 0 offset enable 0 1 abc enable 1 0 arbitrary timing (all readout lines) 1 1 arbitrary timing (valid lines only) note) * : don't care maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
MN86075 7 sde00009bem pin name i/o pin no. function npeak1 o 44 gain control signal 1 (overflow 1) low: gain reduced. high: gain increased. npeak2 o 43 gain control signal 2 (overflow 2) low: gain reduced. high: gain increased. clamp o 45 clamp (offset correction) period signal low: hold high: sample (offset adjustment operation) abc o 46 valid abc period signal low: gain held high: gain adjustment pin descriptions (continued) 5. sensor drive pins (4 pins) pin name i/o pin no. function nvreq i 47 video request inputs image data transfer requests from the control device. low: transfer requests enabled high: transfer requests disabled in trigger scan mode, when this pin is set low, the sensor start signal (stpl) goes low and a sensor readout operation starts. then, one line of image processing is performed and the image data is output from the vsda pin. in cycle scan mode, when this pin is set low, the next readout line is taken to be valid, one line of image processing is performed, and the image data is output from the vsda pin. in free scan mode, the state of this pin is ignored. sensor readout is started at the period specified for the timing, the image processing for each line is performed, and the data is output from the vsda pin. dreq o 49 parallel mode ipara: 1 (ibcnt reg) parallel data send request low: send requests disabled. high: send requests enabled. nvsen o serial mode ipara: 0 (ibcnt reg) video enable low: image data valid period high: image data invalid period ndack i 48 parallel data acknowledge input data send acknowledge signal for dreq low: data send acknowledge enable high: data send acknowledge disable 6. image bus interface pins (5 pins) maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
MN86075 8 sde00009bem pin name i/o pin no. function vsck o 50 parallel mode ipara: 1 (ibcnt reg) video serial clock (external circuit support signal) vsda data acquisition timing nvsck o serial mode ipara: 0 (ibcnt reg) video serial clock vsda data acquisition timing vsda o 51 parallel mode ipara: 1 (ibcnt reg) video serial data (external circuit support signal) output for two-valued image data low: white, high: black nvsda o serial mode ipara: 0 (ibcnt reg) video serial data output for two-valued image data low: black, high: white pin descriptions (continued) 6. image bus interface pins (5 pins) (continued) pin name i/o pin no. function vadd7 i 52 psd2 : 0, psd1 : 0, psd0 : * (ibcnt reg) external a/d converter signal input nhrocs o psd2 : 0, psd1 : 1, psd0 : * (ibcnt reg) shading rom chip select vpd7 o/hi-z psd2 : 1, psd1 : 0, psd0 : 0 (ibcnt reg) two-valued parallel image output (parallel interface) ndack: low: output mode ndack: high: high impedance vscd7 o psd2 : 1, psd1 : 0, psd0 : 1 (ibcnt reg) shading correction image signal output ckvg o psd2 : 1, psd1 : 1, psd0 : 0 (ibcnt reg) multivalued image signal period clock output sbus7 o psd2 : 1, psd1 : 1, psd0 : 1 (ibcnt reg) internal dbus data output 7. parallel i/o pins (8 pins) note) * : don't care maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
MN86075 9 sde00009bem pin name i/o pin no. function vadd6 i 53 psd2 : 0, psd1 : 0, psd0 : * (ibcnt reg) external a/d converter signal input hkwr o psd2 : 0, psd1 : 1, psd0 : 0 (ibcnt reg) hmkd read/write output vpd6 o/hi-z psd2 : 1, psd1 : 0, psd0 : 0 (ibcnt reg) two-valued parallel image signal output (parallel interface) ndack: low: output mode ndack: high: high impedance vscd6 o psd2 : 1, psd1 : 0, psd0 : 1 (ibcnt reg) shading correction image signal output vgsd6 o psd2 : 1, psd1 : 1, psd0 : 0 (ibcnt reg) multivalued image signal output sbus6 o psd2 : 1, psd1 : 1, psd0 : 1 (ibcnt reg) internal dbus data output vadd5 i 54 psd2 : 0, psd1 : 0, psd0 : * (ibcnt reg) external a/d converter signal input nhrstk o psd2 : 0, psd1 : 1, psd0 : * (ibcnt reg) black shading external address counter clear vpd5 o/hi-z psd2 : 1, psd1 : 0, psd0 : 0 (ibcnt reg) two-valued parallel image signal output (parallel interface) ndack: low: output mode ndack: high: high impedance vscd5 o psd2 : 1, psd1 : 0, psd0 : 1 (ibcnt reg) shading correction image signal output vgsd5 o psd2 : 1, psd1 : 1, psd0 : 0 (ibcnt reg) multivalued image signal output sbus5 o psd2 : 1, psd1 : 1, psd0 : 1 (ibcnt reg) internal dbus data output vadd4 to i 55 to 59 psd2 : 0, psd1 : 0, psd0 : * (ibcnt reg) vadd0 external a/d converter signal input hmkd4 to i/o psd2 : 0, psd1 : 1, psd0 : * (ibcnt reg) hmkd0 black shading correction data input and output hkwr: low: input hkwr: high: output vpd4 to o/hi-z psd2 : 1, psd1 : 0, psd0 : 0 (ibcnt reg) vpd0 two-valued parallel image signal output (parallel interface) ndack: low: output mode ndack: high: high impedance vscd4 to o psd2 : 1, psd1 : 0, psd0 : 1 (ibcnt reg) vscd0 shading correction image signal output pin descriptions (continued) 7. parallel i/o pins (8 pins) (continued) note) * : don't care maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
MN86075 10 sde00009bem pin name i/o pin no. function vgsd4 to o 55 to 59 psd2 : 1, psd1 : 0, psd0 : 0 (ibcnt reg) vgsd0 (continued) multivalued image signal output sbus4 to o psd2 : 1, psd1 : 1, psd0 : 1 (ibcnt reg) sbus0 internal dbus data output pin descriptions (continued) 7. parallel i/o pins (8 pins) (continued) note) (1) vpd0 to vpd7 1: black - data direction: msb first 0: white (2) vgsd0 to vgsd7 ff: white to 00: black (3) vgsd0 to vgsd6 7f: white to 00: black (4) vadd0 to vadd7 ff: white to 00: black 8. memory interface pins (57 pins) mode pins: mcm0, mcm1 the function is selected by rsh, mag, stk, and exscd in the memory control register (mecr) mode pins mecr image-processing function mode shading other items mcm1 mcm0 rsh mag l low low 0 0 image signal frequencies maximum: 625 khz to 2.0 mhz 01 stk (memory selection) 0: sram or psram 1 0 rom 1: psram fixed exscd ? 0: internal scd processing 1 1 rom 1: external scd input fixed m low high 0 * image signal frequencies maximum: 4.0 mhz exscd ? 0: internal scd processing 1: external scd input 1 1 rom stk: * fixed a system structure using only two srams is possible if black correction and enlargement processing are not used. note) : can be performed : can not be performed ? : scd: shading-corrected data * : don't care white correction black correction enlargement processing maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
MN86075 11 sde00009bem mode pins mecr image-processing function mode shading other items mcm1 mcm0 rsh mag h high high ** image signal frequencies rom maximum: 12.5 mhz fixed exscd ? 0: internal scd processing 1: external scd input stk : * pin descriptions (continued) 8. memory interface pins (57 pins) (continued) white correction black correction enlargement processing pin name i/o pin no. function lmxd0 to i/o 18 to ram data i/o lmxd7 11 i/o of white shading data, black shading data, error diffusion processing error data, and two-line image data. lma0 to o 95 to ram address lma7 88 lma8 97 lma9 96 lma10 104 lma11 103 lma12 102 lma13 2 lma14 105 nlmoe o 99 ram oe control nlmwe o 100 ram we control nlmce o 101 pseudo sram cs control lsid0 to i 103 to white shading rom data input or lsid7 106 external shading-corrected data input. nlroe o 98 white shading rom oe control nlrwe o 4 eerom we control lra10 to o 116 to eerom address high-order bits lra12 114 (lma0:9 are used for the low-order bits of the address.) lap0 to o 127 to output port a (8 bits) lap6 121 lap7 10 lbp0 to o 9 to output port b (8 bits) lbp4 5 lbp5 120 lbp6 119 lbp7 118 8.1. l mode note) : can be performed ? : scd: shading-corrected data * : don't care maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
MN86075 12 sde00009bem pin descriptions (continued) 8.2. m mode pin name i/o pin no. function mmed0 to i/o 18 to ram data i/o mmed7 11 white shading data and error diffusion processing error data mmfd0 to i/o 127 to ram data i/o mmfd6 121 black shading data and error diffusion processing error data (for enlargement) mmfd7 10 mmld0 to i/o 120 to ram data i/o mmld6 114 input and output of two-line image data msid0 to i 113 to white shading rom data input or msid7 106 external shading-corrected data input mma0 to o 95 to ram address mma7 88 mma8 97 mma9 96 mma10 to 104 to mma12 102 mma13 6 msa0 o 2 ram address high-order bits msa1 105 nmmewe o 101 ram we control nmmfwe 100 nmmlwe 99 nmmoe o 98 ram oe control nmroe o 5 white shading rom and eerom oe control nmrwe o 4 eerom we control mbp0 to o 9 to 7 output port b (3 bits) mbp2 8.3. h mode pin name i/o pin no. function hmsd0 to i/o 18 to ram data i/o hmsd7 11 white shading data mmad0 to i/o 127 to ram data i/o mmad6 121 input and output of single-line image data mmbd0 to i/o 10 to ram data i/o mmbd6 4 input and output of single-line image data mmcd0 to i/o 120 to ram data i/o mmcd6 114 input and output of single-line image data hmid0 to i 113 to fifo data input hmid7 106 error diffusion processing error data hmod0 to o 95 to fifo data output hmod7 88 error diffusion processing error data maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
MN86075 13 sde00009bem pin descriptions (continued) 8.3. h mode (continued) pin name i/o pin no. function hmswr o 97 ram oe control hmawr 96 hmbwr 104 hmcwr 103 hmwe o 102 ram we control (requires a nand gate.) hwck o 105 fifo wck hrck o 101 fifo rck nhrstw o 100 fifo rstw nhrstr o 99 fifo rstr nhfwe o 98 fifo we mack o 3 ram address counter clock nhrsta o 2 ram address counter clear 9. analog pins (20 pins) pin name i/o pin no. function adin1 i 32 a/d converter inputs adin2 i 31 serial mode - adpara: 0 (adofs reg = sha3) adin1: image signal input adin2: unused (must be connected to avss.) parallel mode - adpara: 1 (adofs reg = sha3) adin1: odd image signal input adin2: even image signal input fetd1 o 36 fet 1 drain fetg1 i 38 fet 1 gate fets1 o 37 fet 1 source fetd2 o 29 fet 2 drain fetg2 i 27 fet 2 gate fets2 o 28 fet 2 source agout1 o 39 gain control circuit 1 - output agur1 o 40 gain control circuit 1 - gain increasing resistor connection agdr1 o 41 gain control circuit 1 - gain reducing resistor connection vinig1 o 42 gain control circuit 1 - initialization control agout2 o 26 gain control circuit 2 - output agur2 o 25 gain control circuit 2 - gain increasing resistor connection agdr2 o 24 gain control circuit 2 - gain reducing resistor connection vinig2 o 23 gain control circuit 2 - initialization control maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
MN86075 14 sde00009bem note) 1. ? : in the following, v ss indicates the voltage applied to v ss , and v dd indicates the voltage applied to v dd . each of the power supply pins must be connected to v dd or v ss . 2. the absolute maximum ratings are limiting values under which the chip will not be destroyed. operation is not guaranteed within these ranges. electrical characteristics 1. absolute maximum ratings at v ss ? = 0.0 v parameter symbol rating unit supply voltage v dd ? 0.3 to + 7.0 v input voltage v in v ss ? 0.3 to v dd + 0.3 v output voltage v o v ss ? 0.3 to v dd + 0.3 v input/output voltage v in v ss ? 0.3 to v dd + 0.3 v v o v ss ? 0.3 to v dd + 0.3 v analog voltage v a v ss ? 0.3 to v dd + 0.3 v power dissipation p t 750 mw operating temperature t op 0 to + 70 c storage temperature t stg ? 55 to + 125 c pin descriptions (continued) 9. analog pins (20 pins) (continued) pin name i/o pin no. function ofhc1 o 20 offset control circuit 1 - capacitor connection 1 ofhc2 o 22 offset control circuit 2 - capacitor connection 2 ofout1 o 19 offset control circuit 1 - source follower output 1 ofout2 o 21 offset control circuit 2 - source follower output 2 2. operating conditions at v ss = 0.0 v, v dd = 4.75 v to 5.25 v, t a = 0 c to 70 c parameter symbol conditions min typ max unit supply voltage v dd 4.75 5.00 5.25 v external clock frequency clock frequency f cp h mode ?? 25 mhz m mode ?? 32 l mode ?? 32 maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
MN86075 15 sde00009bem electrical characteristics (continued) 3. dc characteristics at v ss = 0.0 v, v dd = 4.75 v to 5.25 v, t a = 0 c to 70 c parameter symbol conditions min typ max unit supply current, h mode, f cp = 25 mhz supply current i dd when f cp = 25 mhz ? 50 100 ma clock input pin nmclki high-level input voltage v ih1 0.8 v dd ? v dd v low-level input voltage v il1 v ss ? 0.8 v input leakage current i lk1 v in = 0 v to 5 v ?? 10 a digital input pins nvreq, ndack, nwr, nrd, ncs, c80_68, a1, a0, mcm1, mcm0, mast, hmid0 to hmid7 high-level input voltage v ih2 0.7 v dd ? v dd v low-level input voltage v il2 v ss ? 0.8 v input leakage current i lk2 v in = 0 v to 5 v ?? 10 a digital input pins (with built-in schmitt trigger circuit) nreset high-level input voltage v ih3 v dd ? 0.8 ? v dd v low-level input voltage v il3 v ss ? 0.8 v input leakage current i lk3 v in = 0 v to 5 v ?? 10 a digital output pins nhrsta, mack, npeak1, npeak2, clamp, abc, dreq, vsck, vsda, sentim, fr1, fr2, fsg, hmod0 to hmod7, hswr, hawr, hbwr, hcwr, nhfwe, nhrstr, nhrstw, hrck, hwck high-level output voltage v oh4 i oh4 = ? 2.0 ma v dd ? 0.4 ? v dd v low-level output voltage v ol4 i ol4 = 2.0 ma v ss ? 0.4 v leakage current i lk4 v in = 0 to v dd ?? 10 a in the high-impedance state digital output pins fck1, fck2 high-level output voltage v oh5 i oh5 = ? 2.5 ma v dd ? 0.4 ? v dd v low-level output voltage v ol5 i ol5 = 2.5 ma v ss ? 0.4 v leakage current i lk5 v in = 0 to v dd ?? 10 a in the high-impedance state digital i/o pins hmsd0 to hmsd7, hmad0 to hmad6, hmbd0 to hmbd6, hmcd0 to hmcd6, vpd0 to vpd7, nsync, d0 to d7 high-level input voltage v ih6 0.7 v dd ? v dd v low-level input voltage v il6 v ss ? 0.8 v high-level output voltage v oh6 i oh5 = ? 2.0 ma v dd ? 0.4 ? v dd v low-level output voltage v ol6 i ol5 = 2.0 ma v ss ? 0.4 v leakage current i lk6 v in = 0 to v dd ?? 10 a in the high-impedance state maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
MN86075 16 sde00009bem electrical characteristics (continued) 4. ac characteristics at v dd = 5.0 v, v ss = 0.0 v, v ih = 0.7 v dd ? , v il = 0.8 v, v oh = 0.7 v dd , v ol = 0.2 v dd , t a = 0 c to 70 c parameter symbol conditions min typ max unit 1) clock timing h mode nmclk cycle time t mcyc_h load: 50 pf 40 ?? ns h mode nmclk high-level pulse width t mchw_h (with the same 20 ?? ns h mode nmclk low-level pulse width t mclw_h conditions for 20 ?? ns m mode nmclk cycle time t mcyc_m the following 31 ?? ns m mode nmclk high-level pulse width t mchw_m items of ac 15.5 ?? ns m mode nmclk low-level pulse width t mclw_m characteristics.) 15.5 ?? ns l mode nmclk cycle time t mcyc_l 31 ?? ns l mode nmclk high-level pulse width t mchw_l 15.5 ?? ns l mode nmclk low-level pulse width t mclw_l 15.5 ?? ns nmclk falling edge to sync setup time t syis 10 ?? ns nmclk falling edge to sync hold time t syih 10 ?? ns nmclk falling edge to sync delay time t syod ?? 20 ns 2) image bus interface (parallel mode) dreq delay time t dreql ?? 50 ns vpd delay time t vpdd1 ?? 40 ns vpd hold time t vpdh1 10 ?? ns 3) image bus interface (serial mode) nvsck rising edge to nvsen rising edge delay time t vsel ? 0 10 ns nvsck rising edge to nvsen falling edge delay time t vseh ? 0 10 ns nvsck rising edge to nvsda falling edge delay time t vsdh ? 0 10 ns nvsck rising edge to nvsda falling edge delay time t vsdl ? 0 10 ns 4) 68 family cpu interface nwr cycle time t cyce 80 ?? ns nwr pulse width t pwe 40 ?? ns address setup time t as 40 ?? ns address hold time t ah 10 ?? ns data output delay time t ddr ?? 50 ns data output hold time t dhr 10 ?? ns data input setup time t dsw 20 ?? ns data input hold time t dhw 10 ?? ns note) ? : this is v dd ? 0.8 v for the nreset pin, and 0.8 v dd for the nmclki pin. maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
MN86075 17 sde00009bem electrical characteristics (continued) 4. ac characteristics at v dd = 5.0 v, v ss = 0.0 v, v ih = 0.7 v dd ? , v il = 0.8 v, v oh = 0.7 v dd , v ol = 0.2 v dd , t a = 0 c to 70 c (continued) parameter symbol conditions min typ max unit 5) 80x86 family cpu interface address setup time t ar 20 ?? ns address hold time t ra 10 ?? ns data output delay time t rd ?? 50 ns data output hold time t dr 10 ?? ns read pulse width t rw 50 ?? ns address setup time t aw 20 ?? ns address hold time t wa 10 ?? ns data input delay time t wd 10 ?? ns data input hold time t dw 10 ?? ns write pulse width t ww 50 ?? ns 6) memory interface timing (l mode) (maximum = 2.0 mhz, mclk = 32 mhz) t acc = 15 ns mclk to nlmce delay time t mced ?? 10 ns mclk to nlmwe delay time t mwed ?? 10 ns mclk to nlmoe delay time t moed ?? 10 ns mclk to lma delay time t lmad ?? 10 ns mclk to lmxd input setup time t mxis 5 ?? ns mclk to lmxd input hold time t mxih 10 ?? ns nlmoe rising edge to lmxd output delay time t oemd ?? 20 ns (l mode, mag : 0, stk : 1, rsh : 0 or 1) pseudo sram : t acc = 15 ns nlmce high-level pulse width t mcewh1 t mcyc 1.5 ?? ns ? 5 nlmce falling edge to nlmwe rising edge t mcwd1 ?? t mcyc 2ns delay time + 10 lma13-lma14 to nlmwe rising edge t lmwed1 ?? t mcyc 1.5 ns delay time + 5 nlmwe low-level pulse width t mwewl1 t mcyc ? 10 ?? ns nlmwe rising edge to lmxd output hold time t mxoh1 10 ?? ns (l mode, mag : 0, stk : 0, rsh : 0 or 1) pseudo sram : t acc = 15 ns nlmce high-level pulse width t mcewh2 t mcyc ? 5 ?? ns nlmce low-level pulse width t mcewl2 t mcyc 1.5 ?? ns ? 5 nlmce falling edge to nlmwe rising edge t mcwd2 ?? t mcyc 1.5 ns delay time + 5 note) ? : this is v dd ? 0.8 v for the nreset pin, and 0.8 v dd for the nmclki pin. maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
MN86075 18 sde00009bem electrical characteristics (continued) 4. ac characteristics at v dd = 5.0 v, v ss = 0.0 v, v ih = 0.7 v dd ? , v il = 0.8 v, v oh = 0.7 v dd , v ol = 0.2 v dd , t a = 0 c to 70 c (continued) parameter symbol conditions min typ max unit (l mode, mag : 0, stk : 0, rsh : 0 or 1) (continued) pseudo sram : t acc = 15 ns nlmwe low-level pulse width t mwewl2 t mcyc 1.5 ?? ns ? 10 nlmwe rising edge to lmxd output hold time t mxoh2 10 ?? ns (l mode, mag : 1, stk : 0, rsh : * ) pseudo sram : t acc = 15 ns nlmce high-level pulse width t mcewh3 t mcyc /2 ?? ns ? 5 nlmce high-level pulse width 1 t mcewl3 t mcyc 1.5 ?? ns ? 10 nlmce low-level pulse width 2 t mcewl32 t mcyc ? 10 ?? ns nlmce falling edge to nlmwe rising edge t mcwd3 ?? t mcyc ns delay time + 5 nlmwe low-level pulse width t mwewl3 t mcyc ? 5 ?? ns nlmwe falling edge to lmxd output hold time t mxoh3 10 ?? ns (l mode, mag : 0, stk : 1, rsh : * ) pseudo sram : t acc = 15 ns nlmce high-level pulse width t mcewh4 t mcyc ? 10 ?? ns nlmce falling edge to nlmwe rising edge t mcwd4 ?? t mcyc 1.5 ns delay time + 5 lma12-lma14 to nlmwe rising edge t lmwed4 ?? t mcyc ns delay time + 5 nlmwe low-level pulse width t mwewl4 t mcyc /2 ?? ns ? 5 nlmwe rising edge to lmxd output hold time t mxoh4 10 ?? ns (l mode, mag : 0, stk : 0, rsh : 0 or 1 ; sram) (maximum 2.0 mhz, mclk = 32 mhz) sram : t acc = 15 ns lma ? nlmwe falling edge delay time t lmwed5 ?? t mcyc ns + 5 nlmwe low-level pulse width t mwewl5 t mcyc 1.5 ?? ns ? 10 nlmwe rising edge to lma output hold time t lmoh5 t mcyc /2 ?? ns ? 5 nlmwe rising edge to lmxd output hold time t mxoh5 t mcyc /2 ?? ns ? 5 note) ? : this is v dd ? 0.8 v for the nreset pin, and 0.8 v dd for the nmclki pin. maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
MN86075 19 sde00009bem electrical characteristics (continued) 4. ac characteristics at v dd = 5.0 v, v ss = 0.0 v, v ih = 0.7 v dd ? , v il = 0.8 v, v oh = 0.7 v dd , v ol = 0.2 v dd , t a = 0 c to 70 c (continued) parameter symbol conditions min typ max unit (l mode, mag : 1, stk : 0, rsh : 0 or 1) sram : t acc = 15 ns lma to nlmwe falling edge delay time t lmwed6 ?? t mcyc /2 ns ? 5 nlmwe low-level pulse width t mwewl6 t mcyc ? 10 ?? ns nlmwe rising edge to lma output hold time t lmoh6 10 ?? ns nlmwe rising edge to lmxd output hold time t mxoh6 10 ?? ns (m mode) (maximum 4 mhz, mclk = 32 mhz) sram : t acc = 30 ns mclk rising edge to ckvd output delay time t ckvm ?? 10 ns mclk rising edge to t mma ?? 10 ns mma0-mma13 msa0-msa1 output delay time mclk falling edge to t mxism 5 ?? ns nmmld0-nmmld6 input setup time nmmed0-nmmed7 nmmfd0-nmmfd7 mclk falling edge to t mxihm 10 ?? ns nmmld0-nmmld6 input hold time nmmed0-nmmed7 nmmfd0-nmmfd7 mma0-mma13 to t mawe t mcyc /2 ?? ns nmmlwe falling edge output setup time ? 5 nmmewe falling edge nmmfwe falling edge mclk falling edge to t mwed ?? 15 ns mmlwe falling edge output delay time mmewe falling edge mmfwe falling edge mclk rising edge to nmmoe output delay time t mmoed ?? 15 ns nmmlwe low-level pulse width t mlwew t mcyc 2 ?? ns nmmewe ? 10 nmmfwe nmmlwe rising edge to nmmld0-nmmld6 t mxohm t mcyc /2 ?? ns output hold time ? 5 nmmewe rising edge to nmmed0-nmmed7 nmmfwe rising edge to nmmfd0-nmmfd7 nmmoe rising edge to t oemdm ?? 20 ns nmmld0-nmmld6 output delay time nmmed0-nmmed7 nmmfd0-nmmfd7 note) ? : this is v dd ? 0.8 v for the nreset pin, and 0.8 v dd for the nmclki pin. maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
MN86075 20 sde00009bem electrical characteristics (continued) 4. ac characteristics at v dd = 5.0 v, v ss = 0.0 v, v ih = 0.7 v dd ? , v il = 0.8 v, v oh = 0.7 v dd , v ol = 0.2 v dd , t a = 0 c to 70 c (continued) parameter symbol conditions min typ max unit (h mode) (maximum 12.5 mhz, mclk = 25 mhz) sram : t acc = 15 ns mclk to mack output delay time t macd ?? 15 ns mclk to nhrsta o utput delay time t stad ?? 15 ns mclk to hmwe output delay time t hmwed ?? 15 ns mclk rising edge to t mxish 10 ?? ns hmsd0-hmsd7 input setup time hmad0-hmad6 hmbd0-hmbd6 hmcd0-hmcd6 mclk rising edge to t mxihh 15 ?? ns hmsd0-hmsd7 input hold time hmad0-hmad6 hmbd0-hmbd6 hmcd0-hmcd6 mclk rising edge to t hwrd ?? 15 ns hswr output delay time hawr hbwr hcwr hswr rising edge to hmsd0-hmsd7 t hwrmd ?? 15 ns output delay time hawr rising edge to hmad0-hmad6 hbwr rising edge to hmbd0-hmbd6 hcwr rising edge to hmcd0-hmcd6 hmwe pulse width t hmww t mcyc ? 5 ?? ns 7) fifo memory interface nmclki rising edge to hwck or hrck t mhl ?? 15 ns falling edge output delay time nmclki falling edge to ck or hrck t mhh ?? 15 ns rising edge output delay time hwck falling edge to hrstw falling edge t hsl ?? 8ns output delay time hrck falling edge to hrstr falling edge hwck falling edge to hrstw rising edge t hsh ?? 8ns output delay time hrck falling edge to hrstr rising edge hwck or hrck low-level pulse width t hlw t mcyc /2 ?? ns ? 5 hwck or hrck high-level pulse width t hhw t mcyc /2 ?? ns ? 5 note) ? : this is v dd ? 0.8 v for the nreset pin, and 0.8 v dd for the nmclki pin. maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
MN86075 21 sde00009bem electrical characteristics (continued) 4. ac characteristics at v dd = 5.0 v, v ss = 0.0 v, v ih = 0.7 v dd ? , v il = 0.8 v, v oh = 0.7 v dd , v ol = 0.2 v dd , t a = 0 c to 70 c (continued) parameter symbol conditions min typ max unit 7) fifo memory interface (continuted) hwck falling edge to hfwe falling edge t hwl ?? 8ns output delay time hwck falling edge to hfwe falling edge t hwh ?? 8ns output delay time hwck falling edge to hmod0-hmod7 t hod ?? 8ns output delay time hrck rising edge to hmid0-hmid7 t his ?? 10 ns setup time hrck rising edge to hmid0-hmid7 t hih ?? 0ns hold time 8) multivalued output interface nmclki rising edge to ckvg falling edge t mgl ?? 15 ns output delay time nmclki falling edge to ckvg rising edge t mgh ?? 15 ns output delay time ckvg low-level pulse width t glw t mcyc /2 ?? ns ? 5 ckvg high-level pulse width t ghw t mcyc /2 ?? ns ? 5 ckvg rising edge to vgsd6-vgsd0 t gsd ?? 10 ns output delay time 9) ccd sensor interface nmclki falling edge to fck1 falling edge t mf1l ?? 15 ns output delay time nmclki falling edge to fck1 rising edge t mf1h ?? 15 ns output delay time nmclki falling edge to fck2 falling edge t mf2l ?? 15 ns output delay time nmclki falling edge to fck2 rising edge t mf2h ?? 15 ns output delay time nmclki rising edge to fr1 rising edge t mr1h ?? 15 ns output delay time nmclki rising edge to fr1 falling edge t mr1l ?? 15 ns output delay time nmclki rising edge to fr2 rising edge t mr2h ?? 15 ns output delay time note) ? : this is v dd ? 0.8 v for the nreset pin, and 0.8 v dd for the nmclki pin. maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
MN86075 22 sde00009bem electrical characteristics (continued) 4. ac characteristics at v dd = 5.0 v, v ss = 0.0 v, v ih = 0.7 v dd ? , v il = 0.8 v, v oh = 0.7 v dd , v ol = 0.2 v dd , t a = 0 c to 70 c (continued) 5. analog characteristics at v dd = 5.0 v, v ss = 0.0 v, t a = 25 c parameter symbol conditions min typ max unit a/d converter resolution res ?? 8 bit linearity error el f = 0.1 mhz to 12.5 mhz ? 0.5 0.9 lsb differential linearity error ed v refh = 4.0 v, v refl = 1.0 v ? 0.5 0.9 lsb reference voltage high level v refh 1.6 ? v dd v reference voltage low level v refl v ss ? 3.4 v reference voltage low to high v refhl 1.6 ? v dd v level difference reference ladder resistor r ref v refhl = 3.0 v 300 450 ?? offset voltage low side v adoff v refhl = 3.0 v 0 ? 150 mv fet minimum channel resistance r cho v fetg = 5.0 v, v fets = 1.5 v 20 30 60 ? v fetd = 1.7 v gate leakage current i fetg v fetg = v ss , v agout = v dd ?? 100 na v fetg = v dd , v agout = v ss fet gate control analog switch agout to fetg on-resistance r fet v agout = 2.5 v, v fetg = 3.0 v ?? 1.0 k ? agout to fetg off-leakage i agl v agout = 2.5 v, v fetg = 3.0 v ?? 100 na abc control analog switch agdr to agout on-resistance r dr v agout = 2.5 v, v agdr = 3.0 v ?? 300 ? agur to agout on-resistance r ur v agout = 2.5 v, v agur = 2.0 v ?? 300 ? vinig to agout on-resistance r inig v agout = 2.5 v, v inig = 3.0 v ?? 300 ? parameter symbol conditions min typ max unit 9) ccd sensor interface (continuted) nmclki rising edge to fr2 falling edge t mr2l ?? 15 ns output delay time fr1 falling edge to fck1 falling edge or fr2 t r1fm ?? 0ns rising edge output delay time fr2 falling edge to fck1 riging edge or fr2 t r2fm ?? 0ns falling edge output delay time fck1 rising edge to fck2 falling edge or fck1 t fc12 ?? 5ns falling edge to fck2 rising edge output delay time note) ? : this is v dd ? 0.8 v for the nreset pin, and 0.8 v dd for the nmclki pin. maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
MN86075 23 sde00009bem electrical characteristics (continued) 5. analog characteristics at v dd = 5.0 v, v ss = 0.0 v, t a = 25 c (continued) parameter symbol conditions min typ max unit abc control analog switch (continued) agout off leakage current i agout v agout = v dd , v inig = v ss ?? 100 na v agdr = v ss , v agur = v ss v agout = v ss , v inig = v dd v agdr = v dd , v agur = v dd offset control analog switch ofhc charge resistance r ofu v ofhc = 2.5 v ? 9.5 20.0 k ? ofhc discharge resistance r ofd v ofhc = 2.5 v ? 11.5 20.0 k ? ofhc off leakage current i ofhc v ofhc = v dd or v ofhc = v ss ?? 100 na offset control fet ofout on current i dsout v ofhc = v dd , v ofout = 3.0 v 1.0 3.7 ? ma ofout off leakage current i ofout v ofhc = v ss , v ofout = 2.5 v ?? 100 na maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
MN86075 24 sde00009bem package dimensions (unit: mm) ? lqfp128-p-1818c (lead-free package) (1.25) (1.25) 18.00 0.10 18.00 0.10 20.00 0.20 20.00 0.20 0.20 0.05 1.40 0.10 1.70 max. 0.10 0.10 (0.60) 0.15 0.05 (1.00) 0.50 0.20 128 97 1 32 33 64 65 96 seating plane 0 to 10 0.50 m 0.10 0.10 0.25 maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
request for your special attention and precautions in using the technical information and semiconductors described in this book (1) if any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed. (2) the technical information described in this book is intended only to show the main characteristics and application circuit examples of the products, and no license is granted under any intellectual property right or other right owned by our company or any other company. therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other company which may arise as a result of the use of technical information described in this book. (3) the products described in this book are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). consult our sales staff in advance for information on the following applications: ? special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the prod- ucts may directly jeopardize life or harm the human body. ? any applications other than the standard applications intended. (4) the products and product specifications described in this book are subject to change without notice for modification and/or im- provement. at the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date product standards in advance to make sure that the latest specifications satisfy your requirements. (5) when designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions (operating power supply voltage and operating environment etc.). especially, please be careful not to exceed the range of absolute maximum rating on the transient state, such as power-on, power-off and mode-switching. otherwise, we will not be liable for any defect which may arise later in your equipment. even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (6) comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (esd, eos, thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. when using products for which damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages. (7) this book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of matsushita electric industrial co., ltd. maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/

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